Wiki Verilog language wire, reg, and logic

wire, reg, and logic

What you can drive with assign vs always, and why SV logic replaces both.

In Verilog, the type answers “who drives this net?”, not “is it a flip-flop?”.

flowchart TB
  assign_blk[assign] --> wire_n[wire]
  always_blk[always] --> reg_n[reg]
  sv[SystemVerilog] --> logic_n[logic]

Type	Driven by	Typical use
`wire`	`assign`, instance output	Combo nets, port interconnect
`reg`	procedural `always` / `initial`	Flops or combo in `always @*`
`logic` (SV)	either	Prefer in new RTL

A reg is not automatically a flip-flop. always @(posedge clk) q <= d is a flop; always @* q = a & b is combo stored in a reg variable.

Wrong vs right

Wrong — declare an assign target as reg:

reg y;
assign y = a & b;  // illegal

Right — match the driver:

wire y;
assign y = a & b;

Or in SystemVerilog: logic y; and pick assign or always_comb.