Modules and ports

Instantiation, named port maps, and hierarchy.

A module is a hardware hierarchy node. Prefer named port connections so reordering ports cannot silently swap wires.

flowchart TB
  top[top] --> mid[mid]
  mid --> leaf[leaf]

leaf #(.WIDTH(8)) u_leaf (
  .clk (clk),
  .rst_n (rst_n),
  .d   (d),
  .q   (q)
);

Wrong vs right

Wrong — positional ports on a module you did not write this morning:

leaf u_leaf (clk, d, rst_n, q);  // easy to swap

Right — named maps, parameters via #().

Instance names (u_leaf) show up in waves and lint; keep them stable.