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Wiki Verilog language Tasks, functions, system tasks

Tasks, functions, system tasks

Combinational functions vs timed tasks, and $readmem / $display.

Functions compute a value with no time. Tasks may consume time (#, @) and belong in testbenches (or rare timed models). System tasks ($display, $readmemb) are simulator services.

flowchart TB
  fn[function] --> combo[zero_time_combo]
  task[task] --> tb[TB_timing]
  sys["$readmem / $display"] --> sim[simulator]
function automatic logic [7:0] rev8(input logic [7:0] x);
  rev8 = {x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7]};
endfunction

A synthesizable function must be automatic (or clearly side-effect free) and must not wait.

Wrong vs right

Wrong — $display / #delay inside the DUT:

always @(posedge clk) begin
  #1;
  $display("q=%h", q);
end

Right — keep system tasks in the TB; use $readmemb to init a memory array from a text file in simulation.

See also