Multiplexers

Combinational 16:1 MUX (32-Bit Datapath)

Combinational 16:1 mux with sixteen 32-bit inputs and a 4-bit select.

Open in IDE Category Wiki · mux / demux

About this block

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Combinational 16:1 MUX (32-Bit Datapath) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This OpenIP implements a 16-to-1 multiplexer with a 32-bit data path. It selects one of sixteen 32-bit input signals based on a 4-bit selection signal. The design is fully combinational and latch-free. It uses a case statement for clear and synthesizable logic.

This IP provides a robust and simple 16-to-1 multiplexer. It is suitable for routing 32-bit data streams. The design is easy to integrate and verify. Simulation results confirm correct functionality.

Choose Open in IDE. RTL Studio loads the packaged workspace for Combinational 16:1 MUX (32-Bit Datapath).
Read the Verilog module in the editor. The catalog line for this block: Combinational 16:1 mux with sixteen 32-bit inputs and a 4-bit select.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports 16 independent 32-bit data inputs. Uses a 4-bit selector for input routing. Combinational logic with no internal state. Default output is zero for undefined selection states.

Ports

Port	Direction	Width	Description
sel	input	[3:0]	Selection signal
d0	input	[31:0]	Data input 0
d1	input	[31:0]	Data input 1
d2	input	[31:0]	Data input 2
d3	input	[31:0]	Data input 3
d4	input	[31:0]	Data input 4
d5	input	[31:0]	Data input 5
d6	input	[31:0]	Data input 6
d7	input	[31:0]	Data input 7
d8	input	[31:0]	Data input 8
d9	input	[31:0]	Data input 9
d10	input	[31:0]	Data input 10

Verification

The testbench covers sequential input selection. It verifies random data at specific indices. It checks edge cases like all identical inputs. It validates zero data and maximum data values. All tests passed successfully in simulation.

Test Case	Description	Result
TC1	Sequential Input Test	PASS
TC2	Random Data Test	PASS
TC3	All Inputs Same Value	PASS
TC4	Zero Data	PASS
TC5	Max Data	PASS

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