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Multiplexers

Combinational 4:1 MUX (3-Bit Datapath)

Combinational 4:1 mux with four 3-bit inputs and a 2-bit select.

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About this block

Simulate it in the Verilog IDE

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Combinational 4:1 MUX (3-Bit Datapath) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A fully synthesizable, latch-free 4-to-1 multiplexer with 3-bit data inputs and 2-bit select lines.

This IP core implements a 4-to-1 multiplexer designed for high reliability and ease of synthesis. It supports 3-bit wide data paths controlled by a 2-bit selector signal. The design uses a case statement with a default case to ensure no latches are inferred, making it suitable for both FPGA and ASIC flows. It has been verified against all 16 select combinations and dynamic input change scenarios.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Combinational 4:1 MUX (3-Bit Datapath).
  2. Read the Verilog module in the editor. The catalog line for this block: Combinational 4:1 mux with four 3-bit inputs and a 2-bit select.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Data Width: 3 bits
  • Select Width: 2 bits
  • Logic Type: Fully combinational, latch-free
  • Language: Verilog-2001
  • Verification: Self-checking testbench included

Ports

Port NameDirectionWidthDescription
d0Input3Data input 0
d1Input3Data input 1
d2Input3Data input 2
d3Input3Data input 3
selInput2Select lines
yOutput3Multiplexed output

Architecture

The module uses a combinational always @(*) block with a case statement. A default case is provided to assign 0 to the output register if an undefined select value occurs, preventing latch inference.

Verification

The included testbench (tb_mux_4to1.v) performs the following checks:

  1. Static Selection: Verifies output matches the selected input for all 16 combinations of sel.
  2. Dynamic Changes: Verifies correct output when data inputs change while sel remains constant.
  3. Self-Checking: Counts errors and displays pass/fail status for each test case.

All test cases are designed to pass successfully under normal operating conditions.

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