Multiplexers

Combinational 4:1 MUX (8-Bit Datapath, Enable)

Combinational 4:1 mux with 8-bit inputs; active-high enable forces zero output.

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About this block

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Combinational 4:1 MUX (8-Bit Datapath, Enable) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This module implements an 8-bit wide 4-to-1 multiplexer. It selects one of four 8-bit input data channels based on a 2-bit select signal (sel). The design includes an active-high enable signal (en) for power management. The implementation is purely combinational and latch-free.

Choose Open in IDE. RTL Studio loads the packaged workspace for Combinational 4:1 MUX (8-Bit Datapath, Enable).
Read the Verilog module in the editor. The catalog line for this block: Combinational 4:1 mux with 8-bit inputs; active-high enable forces zero output.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The core logic uses a case statement to route the selected input to the output. When the enable signal is low, the output is forced to zero. All input bits are processed simultaneously for maximum throughput. The design avoids latches by assigning the output in all case branches.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input (for testbench consistency, unused in logic)
rst_n	Input	1	Active-low reset (for testbench consistency, unused in logic)
sel	Input	2	Select signal for input channel (00=d0, 01=d1, 10=d2, 11=d3)
en	Input	1	Active-high enable signal. Output is zero when low.
d0	Input	8	Data input channel 0
d1	Input	8	Data input channel 1
d2	Input	8	Data input channel 2
d3	Input	8	Data input channel 3
y	Output	8	Multiplexed output data

Verification

The testbench verifies all functional scenarios including disable and dynamic switching.

Test Case 1: Confirms the output is zero when the enable signal is deasserted.
Test Case 2: Verifies correct routing of input d0.
Test Case 3: Verifies correct routing of input d1.
Test Case 4: Verifies correct routing of input d2.
Test Case 5: Verifies correct routing of input d3.
Test Case 6: Performs dynamic switching across all four inputs.

All test cases passed successfully in the simulation log.

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