Multiplexers

Combinational 8:1 MUX (32-Bit Datapath, Enable)

Combinational 8:1 mux selecting one of eight 32-bit words when enabled.

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About this block

Simulate it in the Verilog IDE

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Combinational 8:1 MUX (32-Bit Datapath, Enable) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a fully synthesizable, latch-free 8-to-1 multiplexer with a 32-bit data path. It selects one of eight input words based on a 3-bit select signal (sel) when the active-high enable signal (en) is asserted. When disabled, the output is forced to zero. The design is purely combinational, though it includes clock and reset ports for interface consistency with other IP cores in the system.

The mux_8to1 module provides a simple, efficient mechanism for routing 32-bit data. It is designed to be:

Synthesizable: Uses Verilog-2001 compliant syntax.
Latch-Free: Ensures predictable timing and avoids unintended latches.
Safe Default: Outputs zero when disabled.

Choose Open in IDE. RTL Studio loads the packaged workspace for Combinational 8:1 MUX (32-Bit Datapath, Enable).
Read the Verilog module in the editor. The catalog line for this block: Combinational 8:1 mux selecting one of eight 32-bit words when enabled.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input (not used for logic, kept for consistency)
rst_n	Input	1	Active-low reset (not used for logic, kept for consistency)
en	Input	1	Active-high enable signal. Output is valid only when high.
sel	Input	3	Select signal for input channel (0-7).
d0	Input	32	Data input 0
d1	Input	32	Data input 1
d2	Input	32	Data input 2
d3	Input	32	Data input 3
d4	Input	32	Data input 4
d5	Input	32	Data input 5
d6	Input	32	Data input 6
d7	Input	32	Data input 7

Integration

### Instantiation Example

Verification

The provided testbench tb_mux_8to1.v verifies the following behaviors:

Disable Check: Verifies output is zero when en is low.
Select Check: Verifies output matches specific inputs (d0, d7, d4) based on sel.
Cycle Check: Cycles through all 8 inputs to ensure correct routing.

### Running Simulation

To run the simulation using Icarus Verilog:

Expected output includes:

TC1 PASS - Output is 0 when disabled
TC2 PASS - Output matches d0
TC3 PASS - Output matches d7
TC4 PASS - Output matches d4
TC5 PASS - All inputs cycled correctly
Simulation ends with INFO: PASS

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