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Multiplexers

Registered 1-Bit 2:1 MUX (Packed din[1:0])

Registered 2:1 mux with packed 2-bit din bus, active-high enable, and active-low reset.

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About this block

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Registered 1-Bit 2:1 MUX (Packed din[1:0]) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

The mux_2to1 module is a registered 2-to-1 multiplexer featuring an active-high enable signal and an asynchronous active-low reset. It selects between two data inputs (din[0] or din[1]) based on the sel signal. The selection is only active when en is high; otherwise, the output is forced to zero. The output is registered on the positive edge of the clock, ensuring clean timing analysis and suitability for clock domain crossing applications.

### Key Features

  • Registered Output: Output changes only on the positive edge of clk, simplifying timing closure.
  • Asynchronous Reset: rst_n forces dout to 0 immediately when low.
  • Active-High Enable: en allows for power gating or conditional data flow control.
  • Simple Interface: Minimal port count for easy integration.

This IP provides a robust, registered 2-to-1 multiplexer with an active-high enable signal and an asynchronous active-low reset. The output is registered on the positive edge of the clock, ensuring clean timing analysis and suitability for clock domain crossing applications. The module is fully verified via a self-checking testbench covering all functional states including reset behavior, enable gating, and data selection.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Registered 1-Bit 2:1 MUX (Packed din[1:0]).
  2. Read the Verilog module in the editor. The catalog line for this block: Registered 2:1 mux with packed 2-bit din bus, active-high enable, and active-low reset.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input (positive edge triggered)
rst_nInput1Asynchronous active-low reset
dinInput2Data inputs [1:0]
selInput1Select signal (0 selects din[0], 1 selects din[1])
enInput1Enable signal (active high)
doutOutput1Multiplexed output

Integration

### Instantiation

To integrate this module into your design, use the following Verilog template:

### File Structure

Verification

The provided testbench (tb_mux_2to1.v) is a self-checking testbench that verifies:

  1. Reset Behavior: Output is zero immediately after reset deassertion.
  2. Enable Control: Output is zero when enable is low, regardless of inputs.
  3. Data Selection: Output correctly follows din[sel] when enable is high.

### Running Simulation

  1. Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim, or Vivado).
  2. Compile the design and testbench:
  3. Run the simulation:
  4. Check the log output for the following pass messages:

* TC1 PASS - Reset check passed * TC2 PASS - Enable low check passed * TC3-TC8 PASS - Data selection checks passed * INFO: PASS

A VCD file (sim/dump.vcd) is generated for waveform debugging.

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