Multiplexers

Registered 16:1 MUX (32-Bit Datapath, Active-Low Enable)

Registered 16:1 mux with active-low enable and synchronous capture on clk.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Registered 16:1 MUX (32-Bit Datapath, Active-Low Enable) is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a registered 16-to-1 multiplexer with a 32-bit data path. It selects one of sixteen 32-bit input channels based on a 4-bit selector signal. The output is registered on the positive clock edge when enabled. This module provides a reliable registered multiplexing solution for 32-bit data paths, suitable for data routing applications requiring synchronous selection.

This IP core implements a registered 16-to-1 multiplexer with a 32-bit data path. It selects one of sixteen 32-bit input channels based on a 4-bit selector signal. The output is registered on the positive clock edge when enabled. This module provides a reliable registered multiplexing solution for 32-bit data paths. It is suitable for data routing applications requiring synchronous selection.

Choose Open in IDE. RTL Studio loads the packaged workspace for Registered 16:1 MUX (32-Bit Datapath, Active-Low Enable).
Read the Verilog module in the editor. The catalog line for this block: Registered 16:1 mux with active-low enable and synchronous capture on clk.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16 Input Channels: Supports 16 distinct 32-bit input channels.
Synchronous Output: Output is registered on the positive clock edge.
Active-Low Reset: Asynchronous reset via rst_n.
Active-Low Enable: en_n control signal to hold the last selected value when disabled.
Verified: Verified with Icarus Verilog simulation.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset (0 = Reset)
en_n	Input	1	Active-low enable (0 = Enabled)
sel	Input	4	Channel selector [3:0]
d0-d15	Input	32	Data inputs
q	Output	32	Selected data output

Verification

The testbench (tb/tb_mux_16to1_32bit.v) covers three primary scenarios:

Test Case	Description	Result
TC1	Channel Selection	PASS
TC2	Disable Behavior	PASS
TC3	Reset Behavior	PASS

### Running Simulation

Ensure Icarus Verilog is installed.
Run the simulation script:
Check the Log panel for:

- TC1 PASS - TC2 PASS - TC3 PASS - Simulation ends with INFO: PASS

Inspect signals using the waveform viewer:

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