Multiplexers

Glitch-Free 2:1 Clock Mux

A glitch-free 2:1 clock multiplexer that synchronizes selection signals to prevent output glitches during clock source switching.

Open in IDE Category Wiki · mux / demux

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Glitch-Free 2:1 Clock Mux is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a glitch-free 2:1 clock multiplexer designed for seamless switching between two clock sources without generating output glitches. It is critical for clock domain crossing and maintaining low-power design integrity by preventing race conditions and metastability issues during clock source transitions.

Choose Open in IDE. RTL Studio loads the packaged workspace for Glitch-Free 2:1 Clock Mux.
Read the Verilog module in the editor. The catalog line for this block: A glitch-free 2:1 clock multiplexer that synchronizes selection signals to prevent output glitches during clock source switching.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Glitch-Free Operation: Ensures no glitches on clk_out during switching.
Dual Clock Support: Supports two independent clock inputs (clk_a, clk_b).
Synchronous Selection: Uses synchronous selection logic to avoid metastability.
Race Condition Prevention: Implements gating logic to prevent output glitches.
Verified: Verified with Icarus Verilog simulation.
Simple Interface: Minimal port list for easy integration.

Ports

Port Name	Direction	Width	Description
`clk_a`	Input	1	Primary clock input
`clk_b`	Input	1	Secondary clock input
`sel`	Input	1	Selection control signal (0 selects A, 1 selects B)
`clk_out`	Output	1	Muxed clock output

Architecture

The module synchronizes the selection signal to both clock domains independently. It uses registered selection values (sel_sync_a and sel_sync_b) to ensure stable gating. The output is generated using combinational logic on gated clocks, ensuring that the clock enable signals are stable before the clock edge occurs.

Verification

The testbench verifies correct selection behavior under various conditions:

Switching from clock A to B.
Switching from clock B to A.
Rapid switching scenarios.

### Running Simulation

Ensure Icarus Verilog is installed.
Run the simulation script (if provided) or execute:

### Expected Results

After running the simulation, the Log panel should show:

INFO: Starting TC1 - Select A
INFO: TC1 PASS - clk_out follows clk_a
INFO: Starting TC2 - Switch to B
INFO: TC2 PASS - clk_out follows clk_b
INFO: Starting TC3 - Switch to A
INFO: TC3 PASS - clk_out follows clk_a
INFO: Starting TC4 - Rapid Switch
INFO: TC4 PASS - Rapid switching completed

Test Case	Description	Result
TC1	Select A	PASS
TC2	Switch to B	PASS
TC3	Switch to A	PASS
TC4	Rapid Switch	PASS

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