Multiplexers
One-Hot Select Mux 8:1 — L1 Upgrade
Registered 8-to-1 multiplexer with one-hot select encoding and enable control.
About this block
Simulate it in the Verilog IDE
One-Hot Select Mux 8:1 — L1 Upgrade is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP implements a registered 8-to-1 multiplexer with one-hot select encoding. It provides an active-high enable signal to control data propagation. The design is fully synthesizable and latch-free. It uses a case statement for complete combinational coverage. The output is registered on the positive clock edge. Reset is asynchronous and active-low.
This IP provides a reliable registered multiplexer with one-hot select. It is suitable for simple data routing tasks in digital designs. The design is verified and ready for integration.
- Choose Open in IDE. RTL Studio loads the packaged workspace for One-Hot Select Mux 8:1 — L1 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: Registered 8-to-1 multiplexer with one-hot select encoding and enable control.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 8 input data lines of 1-bit width.
- 3-bit one-hot select signal.
- Registered output with enable control.
- Asynchronous active-low reset.
- Fully synthesizable Verilog.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low reset |
| en | Input | 1 | Enable signal |
| sel | Input | 3 | Select signal [2:0] |
| d | Input | 8 | Data inputs [7:0] |
| q | Output | 1 | Mux output |
Architecture
The module uses a single always block sensitive to the clock and reset. It registers the selected data bit when the enable signal is high. The reset forces the output to zero immediately. The case statement covers all 8 select combinations plus a default.
Verification
The testbench verifies reset behavior and enable functionality. It checks all 8 select combinations for correct data routing. It verifies that data is ignored when enable is low. It confirms output stability when enable toggles. All 11 test cases pass successfully.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset behavior check | PASS |
| TC2 | Enable low check | PASS |
| TC3 | Select 0 check | PASS |
| TC4 | Select 7 check | PASS |
| TC5 | Select 3 check | PASS |
| TC6 | Select 5 check | PASS |
| TC7 | Select 1 check | PASS |
| TC8 | Select 2 check | PASS |
| TC9 | Select 4 check | PASS |
| TC10 | Select 6 check | PASS |
| TC11 | Enable toggle check | PASS |
More in Multiplexers
- 4:1 Priority Mux (One-Hot Select) — L1 Upgrade
- Combinational 16:1 MUX (32-Bit Datapath)
- Combinational 32-Bit 2:1 MUX
- Combinational 4:1 MUX (3-Bit Datapath)
- Combinational 4:1 MUX (8-Bit Datapath, Enable)
- Combinational 8:1 MUX (32-Bit Datapath, Enable)
- Glitch-Free 2:1 Clock Mux
- Registered 1-Bit 2:1 MUX (Packed din[1:0])
- Registered 16:1 MUX (32-Bit Datapath, Active-Low Enable)
- Registered 8-Bit 2:1 MUX with Enable