Multiplexers

Registered 8-Bit 2:1 MUX with Enable

Canonical registered 2:1 lesson IP — synchronous 8-bit mux with enable and active-low reset.

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Registered 8-Bit 2:1 MUX with Enable is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements an 8-bit 2-to-1 multiplexer with synchronous enable and active-low asynchronous reset. It selects between two 8-bit data inputs (din_a and din_b) based on a selection signal (sel). The output is registered and cleared to zero when the enable signal (en) is low or when the reset signal (rst_n) is asserted.

This module is suitable for data path selection in synchronous designs where enable gating is required to reduce power or control data flow.

Choose Open in IDE. RTL Studio loads the packaged workspace for Registered 8-Bit 2:1 MUX with Enable.
Read the Verilog module in the editor. The catalog line for this block: Canonical registered 2:1 lesson IP — synchronous 8-bit mux with enable and active-low reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Width: 8-bit inputs and output.
Clocking: Synchronous operation driven by a single positive clock edge.
Reset: Active-low asynchronous reset (rst_n).
Enable: Synchronous enable control (en). When en is low, the output is forced to zero.
Selection: 1-bit select signal (sel) chooses between din_a (sel=0) and din_b (sel=1).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Synchronous enable (High = Enable, Low = Output=0)
`sel`	Input	1	Selection signal (0 = din_a, 1 = din_b)
`din_a`	Input	[7:0]	Data input A
`din_b`	Input	[7:0]	Data input B
`dout`	Output	[7:0]	Multiplexed output

Architecture

The module uses a single always block triggered by the positive clock edge or the negative reset edge.

Reset Priority: If rst_n is low, dout is immediately cleared to 0.
Enable Check: If reset is inactive, the module checks the en signal.
Selection Logic:

- If en is high, dout updates to din_a if sel is low, or din_b if sel is high. - If en is low, dout is forced to 0.

Verification

The provided testbench (tb_mux_2to1_8bit.v) covers the following scenarios:

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Enable Low Check	PASS
TC3	Sel=0 Check	PASS
TC4	Sel=1 Check	PASS
TC5	Switch A Check	PASS
TC6	Switch B Check	PASS
TC7	Disable Mid-Op Check	PASS
TC8	Re-enable Check	PASS

### Expected Simulation Output

After running the simulation, the Log panel should display:

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