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Multiplexers

Combinational 32-Bit 2:1 MUX

Latch-free combinational 32-bit 2:1 mux with no clock, reset, or enable.

Open in IDE Category Wiki · mux / demux

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Combinational 32-Bit 2:1 MUX is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP provides a simple, efficient, and fully combinational 32-bit 2-to-1 multiplexer. It selects between two 32-bit input vectors (din_a and din_b) based on a single select signal (sel). The design is latch-free, ensuring minimal latency and no unintended storage elements. It is suitable for basic data routing tasks in digital designs and has been verified with a self-checking testbench.

The module routes din_a to dout when sel is low (0), and din_b to dout when sel is high (1). The implementation uses continuous assignment for optimal synthesis results.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Combinational 32-Bit 2:1 MUX.
  2. Read the Verilog module in the editor. The catalog line for this block: Latch-free combinational 32-bit 2:1 mux with no clock, reset, or enable.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The logic is purely combinational. The Mermaid diagram below illustrates the data flow:

Ports

Port NameDirectionWidthDescription
din_aInput[31:0]Data input A
din_bInput[31:0]Data input B
selInput1Select signal (0: select A, 1: select B)
doutOutput[31:0]Multiplexed output

Verification

The provided testbench (tb/tb_mux_2to1_32b.v) validates all functional modes:

  • Selection of input A when sel=0.
  • Selection of input B when sel=1.
  • Random data patterns for both select states.
  • Edge cases including all zeros and all ones.

### Running the Simulation

  1. Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim).
  2. Run the testbench:
  3. Check the console output for PASS/FAIL status.

A VCD file (sim/dump.vcd) is generated for waveform analysis.

### Expected Results

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