Multiplexers

4:1 Priority Mux (One-Hot Select) — L1 Upgrade

4:1 Priority Mux with Valid/Skid Buffer for L1 Cache Upgrade

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4:1 Priority Mux (One-Hot Select) — L1 Upgrade is a Verilog reference block in the Multiplexers catalog. Multiplexers, demultiplexers, and data-path selectors. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4:1 priority multiplexer with a valid/skid buffer interface.

It selects one of four 32-bit data inputs based on a one-hot select signal, where higher index inputs take priority over lower index inputs.

The integrated skid buffer ensures backpressure handling for continuous data streams, preventing data loss when the output is not ready.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4:1 Priority Mux (One-Hot Select) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 4:1 Priority Mux with Valid/Skid Buffer for L1 Cache Upgrade.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4:1 Priority Multiplexing: Supports four 32-bit data inputs (d0-d3).
One-Hot Select: Uses a 4-bit one-hot select signal (sel) for input selection.
Priority Logic: sel[3] > sel[2] > sel[1] > sel[0].
Skid Buffer: Handles backpressure when ready_out is low by storing incoming data.
Valid/Ready Handshake: Provides valid_in/valid_out for flow control.
Reset: Asynchronous active-low reset (rst_n).

Interface

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`sel`	Input	4	One-hot select signal
`d0`	Input	32	Data input 0
`d1`	Input	32	Data input 1
`d2`	Input	32	Data input 2
`d3`	Input	32	Data input 3
`valid_in`	Input	1	Input valid signal
`valid_out`	Output	1	Output valid signal
`ready_out`	Output	1	Ready signal (high if skid is empty)
`dout`	Output	32	Multiplexed output data

Architecture

The module uses a combinational priority mux to determine the selected data. A skid buffer stores data when the output is not ready. The skid buffer drains automatically when the output becomes ready.

Verification

The testbench verifies reset behavior, basic passthrough, priority selection, and skid buffer operations. All test cases passed successfully in the simulation.

Test Case	Description	Result
TC1	Reset State	PASS
TC2	Basic Passthrough (D0)	PASS
TC3	Priority (D2 overrides D0)	PASS
TC4	Skid Drain	PASS
TC5	Skid Fill and Hold	PASS
TC6	Skid Drain after Hold	PASS

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