Parity

Byte-Strobe Parity Scrub 32-bit — L2 Upgrade

SECDED byte-strobe parity scrubber for 32-bit data with SBE/MBE detection.

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About this block

Simulate it in the Verilog IDE

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Byte-Strobe Parity Scrub 32-bit — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a byte-strobe parity scrubber for 32-bit data, designed as an L2 cache upgrade component.

It provides Single Bit Error Detection (SBE) and Multi-Bit Error Detection (MBE) capabilities by monitoring data integrity using per-byte parity and global parity checks.

This ensures robust error detection for cache data paths, identifying both single-byte errors and multi-bit errors that might escape single-bit detection.

Choose Open in IDE. RTL Studio loads the packaged workspace for Byte-Strobe Parity Scrub 32-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: SECDED byte-strobe parity scrubber for 32-bit data with SBE/MBE detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low reset
`byte_strobe`	input	4	Byte write strobe (active high)
`data_in`	input	32	Input data bus
`parity_in`	input	4	Input per-byte parity
`load`	input	1	Load enable signal
`data_out`	output	32	Output data bus (stored data)
`parity_out`	output	4	Output per-byte parity (stored parity)
`sbe_detected`	output	1	Single Bit Error detected (asserted high)
`mbe_detected`	output	1	Multi-Bit Error detected (asserted high)

Verification

The testbench tb_byte_strobe_parity_secded_32.v performs self-checking verification. It validates basic load operations and output consistency. It tests Multi-Bit Error detection with two byte parity mismatches. It confirms no error flags are raised for clean data.

Simulation uses Icarus Verilog and generates a VCD dump.

### Running Simulation

To run the simulation:

Test Case	Description	Expected Result
TC1	Basic Load and Output Check	`data_out` and `parity_out` match inputs; `sbe_detected` low; `mbe_detected` low
TC2	MBE Detection	`mbe_detected` is high, `sbe_detected` is low
TC3	No Error Condition	Both error flags (`sbe_detected`, `mbe_detected`) are low

TC1 data_out PASS
TC1 parity_out PASS
TC2 mbe_detected PASS
TC2 sbe_detected PASS
TC3 sbe_detected PASS
TC3 mbe_detected PASS
Simulation ends with INFO: PASS.

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