Parity

Sticky Parity Error Flag 8-Bit — L1 Upgrade

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Sticky Parity Error Flag 8-Bit — L1 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a sticky parity error flag for 8-bit data buses. It detects odd parity errors on the input data bus (i.e., an odd number of 1s is considered an error for even parity requirements). The error flag remains set until explicitly cleared by a scrub signal or a reset.

This module is suitable for error detection in systems where data integrity is critical, such as communication interfaces or memory buses.

This IP provides a robust sticky parity error detection mechanism for 8-bit data buses. It is fully verified with Icarus Verilog simulation. The design is simple, lightweight, and suitable for integration in systems requiring data integrity checks. It supports synchronous scrubbing for error recovery and asynchronous reset for system initialization.

Choose Open in IDE. RTL Studio loads the packaged workspace for Sticky Parity Error Flag 8-Bit — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Sticky Parity Error Flag 8-Bit — L1 Upgrade.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design uses a reduction XOR tree to compute even parity.

Even Parity: An even number of 1s results in a valid parity state (parity_ok = 1).
Odd Parity: An odd number of 1s triggers the parity error condition (error_flag sets to 1).

The error flag is a register that latches the error state. It can be cleared synchronously via a scrub signal or asynchronously via rst_n.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
data_in	Input	8	Data bus for parity check
scrub	Input	1	Active-high synchronous scrub to clear error
parity_ok	Output	1	High if even parity is detected
error_flag	Output	1	Sticky error flag (latches on odd parity)

Verification

The testbench covers reset behavior and parity checks. It verifies that even parity does not trigger the error flag, while odd parity sets the sticky error flag. It confirms the flag persists when valid data follows an error and checks that the scrub signal clears the error flag. It ensures new errors are detected after a scrub operation.

Test Case	Description	Result
TC1	Reset state check	PASS
TC2	Even parity check	PASS
TC3	Odd parity check	PASS
TC4	Sticky behavior check	PASS
TC5	Scrub clear check	PASS
TC6	New error after scrub	PASS

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