Parity

XOR-Reduce Parity Tree 16-bit

Balanced XOR-reduction tree computing even parity for a 16-bit input vector.

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XOR-Reduce Parity Tree 16-bit is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a balanced XOR-reduction tree for 16-bit data. It computes the even parity bit of the input vector. The design uses a logarithmic depth structure to minimize critical path delay. Simulation confirms correct parity generation for all tested patterns.

This IP provides a fast, balanced parity tree for 16-bit words. It is suitable for error detection in data buses. The design is fully combinational with no clock dependencies. Simulation results confirm functional correctness.

Choose Open in IDE. RTL Studio loads the packaged workspace for XOR-Reduce Parity Tree 16-bit.
Read the Verilog module in the editor. The catalog line for this block: Balanced XOR-reduction tree computing even parity for a 16-bit input vector.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module reduces 16 input bits to a single parity output. It employs a four-level balanced XOR tree topology. Level 1 reduces 16 bits to 8 intermediate signals. Level 2 reduces 8 signals to 4 intermediate signals. Level 3 reduces 4 signals to 2 intermediate signals. Level 4 performs the final XOR to produce the single output bit. This structure ensures O(log N) latency relative to the input width.

Interface

The module has a simple combinational interface.

Signal	Direction	Width	Description
`data_in`	Input	16	Input data vector
`parity_out`	Output	1	Even parity result

Verification

The testbench performs 15 functional test cases. It checks edge cases such as all zeros and all ones. It verifies single-bit transitions and multi-bit patterns. Random patterns are included to ensure robustness. All tests pass successfully in the Icarus Verilog simulator.

Test Case	Input Hex	Expected Parity	Result
TC1	0x0000	0	PASS
TC2	0xFFFF	0	PASS
TC3	0x0001	1	PASS
TC4	0x8000	1	PASS
TC5	0x0003	0	PASS
TC6	0xAAAA	0	PASS
TC7	0x5555	0	PASS
TC8	0x000F	0	PASS
TC9	0x0007	1	PASS
TC10	0x1234	1	PASS
TC11	0x0002	1	PASS
TC12	0x0007	1	PASS

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