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Parity

8-Bit Even/Odd Parity Bit Generator — L1 Upgrade

Generates even parity for 8-bit data and latches a sticky error flag for odd parity occurrences.

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About this block

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8-Bit Even/Odd Parity Bit Generator — L1 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core generates an even parity bit for 8-bit data streams and includes a sticky error flag to detect odd parity conditions. Designed for Level 1 upgrade scenarios, it provides simple, low-latency error detection.

The module uses combinational logic for parity calculation and sequential logic for data latching and error flag management. The sticky error persists until explicitly cleared via a synchronous signal (clear_sticky) or an asynchronous reset (rst_n), ensuring transient faults are not missed.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Even/Odd Parity Bit Generator — L1 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Generates even parity for 8-bit data and latches a sticky error flag for odd parity occurrences.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design comprises two main parts:

  1. Combinational Parity Logic: Computes the XOR reduction of the 8-bit input data immediately.
  2. Sequential Output Registers: Latches the input data and valid signal on the rising clock edge. It also manages the sticky error flag.

### Block Diagram

Ports

Port NameDirectionWidthDescription
clkInput1Clock input for sequential logic
rst_nInput1Active-low asynchronous reset
valid_inInput1Valid input data strobe
data_inInput88-bit data input
clear_stickyInput1Synchronous clear for sticky error. Effective when valid_in is low or on reset.
valid_outOutput1Valid output data strobe
data_outOutput8Output data (latched from data_in)
parity_bitOutput1Calculated parity (0=even, 1=odd)
sticky_errorOutput1Latched error flag for odd parity

Integration

  • Clock Domain: The module operates on a single clock domain (clk).
  • Reset: rst_n is asynchronous and active-low. Ensure reset deassertion is synchronized if crossing clock domains.
  • Latency:

- parity_bit: Zero combinational latency (combinational output). - data_out / valid_out: 1-cycle latency. - sticky_error: Updates 1 cycle after the error condition is detected on valid_in.

  • Clearing Sticky Error: The clear_sticky signal clears the error flag synchronously.

- Important: In the current implementation, the sticky error is only cleared if valid_in is low at the time of the clear request, or if rst_n is asserted. This prevents clearing the error flag during active data transfer to ensure data integrity tracking.

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