Parity
Even Parity over 16-Bit Bus — L1 Upgrade — L2 Upgrade
Hamming(16,11) single-bit error correction module for 16-bit buses with syndrome-based detection and registered output.
About this block
Simulate it in the Verilog IDE
Even Parity over 16-Bit Bus — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements a Hamming(16,11) code for single-bit error correction on a 16-bit bus. It uses even parity syndrome calculation to detect and correct errors. The module supports registered output with reset and read enable control. It is designed for L1 and L2 cache upgrade scenarios requiring data integrity.
This IP provides robust single-bit error correction for 16-bit buses. It uses standard Hamming code principles for efficient implementation. The registered output ensures clean timing for downstream logic. Simulation results confirm correct error detection and correction.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Even Parity over 16-Bit Bus — L1 Upgrade — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: Hamming(16,11) single-bit error correction module for 16-bit buses with syndrome-based detection and registered output.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The design uses a Hamming code structure with 5 parity bits and 11 data bits. Parity bits are located at positions 1, 2, 4, 8, and 16 (indices 0, 1, 3, 7, 15). Syndrome bits are calculated by XORing covered data and parity bits. The syndrome value indicates the 1-based position of the erroneous bit. A correction mask is generated to flip the identified error bit. The corrected data is registered and output when read enable is active.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input for synchronous logic |
| rst_n | Input | 1 | Active-low asynchronous reset |
| data_in | Input | 16 | Input bus containing data and parity bits |
| rd_en | Input | 1 | Read enable signal to update outputs |
| data_out | Output | 16 | Corrected data bus |
| parity_err | Output | 1 | High if a single-bit error was detected and corrected |
Verification
The testbench verifies correct operation under various conditions. It checks for no error cases with zero and non-zero data. It verifies single-bit error correction in data bits and parity bits. It tests reset behavior to ensure outputs go to zero. It confirms error flagging is active during correction events. All six test cases passed successfully in simulation.
| Test Case | Description | Result |
|---|---|---|
| TC1 | No error with zero data | PASS |
| TC2 | Single bit error in data bit | PASS |
| TC3 | Single bit error in parity bit | PASS |
| TC4 | Single bit error in MSB | PASS |
| TC5 | Reset behavior | PASS |
| TC6 | No error with non-zero data | PASS |
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