Parity

Parity-Protected 8-Bit Register — L2 Upgrade

An 8-bit register with 2-bit parity syndrome for single-bit error correction and detection.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Parity-Protected 8-Bit Register — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit register with integrated single-bit error correction for a subset of bits (bits 0, 1, and 2). It uses a 2-bit syndrome mechanism derived from XOR relationships between specific data bits and stored parity bits.

Key Limitations:

Limited Correction: Only errors in data bits 0, 1, and 2 are corrected. Errors in bits 3-7 are detected via err_single but not corrected.
Not Full SEC-DED: This is a lightweight, educational implementation. It does not provide full single-error correction for all 8 data bits.
Parity Storage: The module stores incoming parity bits (parity_in) rather than calculating them. Users must ensure parity_in matches the expected parity of data_in before writing.

The design targets Level 2 complexity for educational purposes and embedded applications where only low-order bits require protection.

Limited Correction: Only errors in data bits 0, 1, and 2 are corrected. Errors in bits 3-7 are detected via err_single but not corrected.
Not Full SEC-DED: This is a lightweight, educational implementation. It does not provide full single-error correction for all 8 data bits.
Parity Storage: The module stores incoming parity bits (parity_in) rather than calculating them. Users must ensure parity_in matches the expected parity of data_in before writing.

Choose Open in IDE. RTL Studio loads the packaged workspace for Parity-Protected 8-Bit Register — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit register with 2-bit parity syndrome for single-bit error correction and detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Storage: Stores 8 bits of data and 2 bits of parity.
Limited Error Correction:

- Syndrome 01 corrects bit 0. - Syndrome 10 corrects bit 1. - Syndrome 11 corrects bit 2. - Other non-zero syndromes indicate errors in bits 3-7 or multi-bit errors, which are flagged but not corrected.

Error Detection: Flags any detected error (single or multi-bit) via the err_single output.
Reset: Resets all internal state to zero on active-low reset.
Interface: Synchronous write, combinational read with enable gating.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous logic.
`rst_n`	Input	1	Active-low asynchronous reset.
`wr_en`	Input	1	Write enable signal.
`rd_en`	Input	1	Read enable signal.
`data_in`	Input	[7:0]	Data input bus.
`parity_in`	Input	[1:0]	Incoming parity bits. Must match expected parity of `data_in`.
`data_out`	Output	[7:0]	Corrected data output (only bits 0-2 are corrected).
`parity_out`	Output	[1:0]	Stored parity output.
`err_single`	Output	1	High if any error is detected (syndrome != 0).
`err_multi`	Output	1	Always low (not supported).

Architecture

The module stores data_in and parity_in when wr_en is asserted. On read (rd_en), it calculates a syndrome by XORing the stored parity with the parity computed from the stored data.

Syndrome Calculation:

syndrome[1] = mem_parity[1] ^ (data[6] ^ data[7])
syndrome[0] = mem_parity[0] ^ (data[4] ^ data[5] ^ data[6] ^ data[7])

Correction Logic:

If syndrome == 2'b01: Flip data[0].
If syndrome == 2'b10: Flip data[1].
If syndrome == 2'b11: Flip data[2].
If syndrome is any other non-zero value: No correction applied, err_single asserted.

Verification

The testbench validates basic write/read cycles, reset functionality, and error correction for bits 0, 1, and 2.

Test Case	Description	Result
TC1	Basic Write/Read with 8'hA5	PASS
TC2	Write/Read with 8'h00	PASS
TC3	Write/Read with 8'hFF	PASS
TC4	Asynchronous Reset	PASS
TC5	Error Correction Bit 0	PASS
TC6	Error Correction Bit 1	PASS
TC7	Error Correction Bit 2	PASS
TC8	Error in Bit 3 (No Correction)	PASS

All tests passed successfully in the Icarus Verilog simulation environment.

More in Parity

All Parity blocks