Parity
8-Bit Parity Error Counter with Accumulator — L2 Upgrade
An 8-bit parity error counter that accumulates odd parity errors in data streams. It supports scrubbing with external data and direct accumulator loading for testing.
About this block
Simulate it in the Verilog IDE
8-Bit Parity Error Counter with Accumulator — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements an 8-bit parity error counter with accumulator support. It detects odd parity errors in 8-bit data streams. It accumulates the total count of detected parity errors. It supports scrubbing to inject corrected data without incrementing the error count. It allows loading a specific accumulator value for testing or reset.
This IP provides a robust solution for tracking parity errors in 8-bit data paths. It supports scrubbing for error correction workflows. It includes accumulator loading for flexible testing. The design is simple and synthesizable. It is suitable for L2 cache error tracking applications.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Parity Error Counter with Accumulator — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: An 8-bit parity error counter that accumulates odd parity errors in data streams. It supports scrubbing with external data and direct accumulator loading for testing.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
The module monitors 8-bit input data for parity errors. It uses even parity checking where odd parity indicates an error. It increments an internal 8-bit accumulator on each detected error. It supports a scrub mode to bypass normal data input. Scrub data is checked for parity independently. Correct scrub data does not increment the error counter. Incorrect scrub data increments the error counter. A load signal allows direct setting of the accumulator value. A reset signal clears the accumulator and status flags.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low reset |
| data_in | Input | 8 | Primary data input |
| valid_in | Input | 1 | Valid data indicator |
| scrub_en | Input | 1 | Scrub enable signal |
| scrub_data | Input | 8 | Scrub data input |
| load_acc | Input | 1 | Load accumulator signal |
| acc_load_val | Input | 8 | Value to load into accumulator |
| acc_out | Output | 8 | Accumulator output |
| parity_err | Output | 1 | Parity error flag |
| scrub_active | Output | 1 | Scrub active indicator |
Architecture
The design consists of a parity checker and an accumulator register. The parity checker evaluates the effective data source. The effective data source is selected by the scrub enable signal. If scrub is enabled, scrub_data is used. Otherwise, data_in is used. The parity bit is calculated using the XOR reduction operator. An odd result indicates a parity error. The accumulator updates on the positive clock edge. It increments only when valid_in is high and a parity error is detected. It updates to acc_load_val when load_acc is high. It holds its value otherwise.
Verification
The testbench verifies reset behavior. It verifies accumulator loading functionality. It verifies parity error detection on normal data. It verifies no increment on correct parity data. It verifies scrub mode with correct data. It verifies scrub mode with incorrect data. It verifies mixed operation scenarios. All tests passed successfully.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset State | PASS |
| TC2 | Load Accumulator | PASS |
| TC3 | Parity Error Detection | PASS |
| TC4 | No Parity Error | PASS |
| TC5 | Scrub Correct Data | PASS |
| TC6 | Increment on Error | PASS |
| TC7 | Mixed Operations | PASS |
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