Parity

Parity Byte Checker 8-Bit — L1 Upgrade — L2 Upgrade

8-bit parity checker with sticky error flag and syndrome-based single-bit correction using data[2:0] as index.

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Parity Byte Checker 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit parity byte checker with sticky error detection and syndrome-based bit correction.

It detects single-bit errors using even parity and corrects them based on a syndrome index derived from the lower 3 bits of the data.

The module registers the input data and control signals to ensure stable output timing.

Choose Open in IDE. RTL Studio loads the packaged workspace for Parity Byte Checker 8-Bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit parity checker with sticky error flag and syndrome-based single-bit correction using data[2:0] as index.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module operates on a rising clock edge with an active-low asynchronous reset. It samples data_in only when a rising edge of rd_en is detected. Parity is computed as the XOR reduction of all 8 input bits. If the parity is odd, an error is flagged and the syndrome index is extracted from data_reg[2:0]. The syndrome index indicates which bit position to flip for correction. This approach assumes a specific error pattern where the error location correlates with the data value's lower bits.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`rd_en`	Input	1	Read enable (rising edge triggers sampling)
`data_in`	Input	8	Input data byte
`parity_ok`	Output	1	High if parity is even (no error)
`err`	Output	1	High if parity is odd (error detected)
`data_out`	Output	8	Corrected output data

Verification

The testbench performs five key test cases to validate functionality.

TC1: Verifies correct operation with even parity data (no error).
TC2: Verifies error detection and correction when syndrome index is 1.
TC3: Verifies error detection and correction when syndrome index is 2.
TC4: Verifies error detection and correction when syndrome index is 4.
TC5: Verifies correct operation with another even parity data pattern.

All tests passed successfully in the Icarus Verilog simulation.

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