Parity

SECDED Hamming Check (13,8)

Single Error Correction Double Error Detection Hamming check for 13-bit codewords.

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SECDED Hamming Check (13,8) is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a Single Error Correction Double Error Detection (SECDED) Hamming check for 13-bit codewords. It accepts 8-bit data and a 5-bit syndrome as inputs. The module determines if a single-bit error or double-bit error has occurred based on the syndrome value and outputs corrected data if a single-bit error is detected.

Note: This implementation assumes a specific mapping where the lower 4 bits of the syndrome directly indicate the bit position within the 8-bit data word for correction. This is a simplified model. For standard Hamming codes, the syndrome typically maps to the full 13-bit codeword position.

This IP provides a lightweight, combinational SECDED check mechanism for 13-bit codewords. It is suitable for memory systems or data paths requiring basic error detection and correction. The implementation relies on direct syndrome bit mapping for simplicity.

Choose Open in IDE. RTL Studio loads the packaged workspace for SECDED Hamming Check (13,8).
Read the Verilog module in the editor. The catalog line for this block: Single Error Correction Double Error Detection Hamming check for 13-bit codewords.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports SECDED logic for 13-bit codewords (8 data bits + 5 parity/syndrome bits).
Detects single-bit errors and corrects them automatically.
Detects double-bit errors without attempting correction.
Identifies valid codewords with no errors.
Simple combinational logic implementation.

Interface

Signal Name	Direction	Width	Description
data_in	Input	[7:0]	Original data input
syndrome_in	Input	[4:0]	Syndrome input including parity bit
sec_err	Output	1	Single Error Correction flag
ded_err	Output	1	Double Error Detection flag
data_out	Output	[7:0]	Corrected data output

Architecture

The module operates as follows:

The core logic evaluates the syndrome input:

If the syndrome is zero, no error is present.
If the syndrome is non-zero and the parity bit (bit 4) is zero, a single-bit error is indicated.
If the syndrome is non-zero and the parity bit (bit 4) is one, a double-bit error is indicated.
For single-bit errors, the data is corrected by XORing with the lower 4 bits of the syndrome.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	No error (syndrome 0)	sec_err=0, ded_err=0, data_out=data_in
TC2	Single bit error (syndrome 1)	sec_err=1, ded_err=0, data_out=corrected
TC3	Double bit error (syndrome with parity bit set)	sec_err=0, ded_err=1, data_out=data_in

All test cases passed in simulation.

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