Parity

8-Bit Parity Generator (Muxed Even/Odd)

Combinational even/odd parity generator using explicit even-parity XOR and mode mux.

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About this block

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8-Bit Parity Generator (Muxed Even/Odd) is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a lightweight, combinational logic module for generating an 8-bit even or odd parity bit.

It accepts an 8-bit data word and a mode selector to determine whether the output parity bit ensures an even or odd total count of 1s.

The design is fully verified, has zero-cycle latency, and is suitable for error detection in data paths.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Parity Generator (Muxed Even/Odd).
Read the Verilog module in the editor. The catalog line for this block: Combinational even/odd parity generator using explicit even-parity XOR and mode mux.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Data Width: Processes 8-bit input vectors.
Configurable Parity: Supports both Even and Odd parity modes via a single control bit.
Combinational Logic: Zero-cycle latency; output updates immediately with input changes.
Verified: Comprehensive testbench covering edge cases (all zeros, all ones, single bit set).

Ports

Port Name	Direction	Width	Description
`data_in`	Input	[7:0]	8-bit input data word
`parity_mode`	Input	1	Mode selector: `0`=Even, `1`=Odd
`parity_out`	Output	1	Computed parity bit

Architecture

The module computes the parity using a reduction XOR operation on the input data.

Even Parity Calculation: The XOR of all bits in data_in is computed. If the count of 1s is even, the result is 0; if odd, the result is 1.
Mode Selection:

- If parity_mode is 0, the even parity result is passed through. - If parity_mode is 1, the even parity result is inverted to produce odd parity.

Verification

The design includes a testbench (tb/tb_parity_gen_8b.v) that verifies functionality against six predefined test vectors covering all modes and edge cases.

Test Case	`data_in`	`parity_mode`	Expected `parity_out`	Description
TC1	0x00	0 (Even)	0	0 ones is even
TC2	0xFF	0 (Even)	0	8 ones is even
TC3	0x01	0 (Even)	1	1 one is odd, parity=1 makes total even
TC4	0x00	1 (Odd)	1	0 ones is even, parity=1 makes total odd
TC5	0xFF	1 (Odd)	1	8 ones is even, parity=1 makes total odd
TC6	0x01	1 (Odd)	0	1 one is odd, parity=0 keeps total odd

### Running the Simulation

To run the simulation, use your preferred Verilog simulator. For example, using Icarus Verilog:

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