Parity

SECDED Nibble Syndrome (toy) — L2 Upgrade

Toy SECDED syndrome calculator for 4-bit nibbles with invalidate and shadow commit support.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

SECDED Nibble Syndrome (toy) — L2 Upgrade is a Verilog reference block in the Parity catalog. Even/odd parity generators, checkers, and error-detection helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

An educational Verilog IP core implementing a Single Error Correction Double Error Detection (SECDED) syndrome calculator for 4-bit nibbles. This module demonstrates byte-enable masking, data invalidation, and atomic shadow-register updates.

This module provides a simple SECDED syndrome calculator for 4-bit data words. It supports:

Standard data writes with byte-enable masking.
Data invalidation.
Atomic shadow register commits.
Syndrome generation for error detection.

It is suitable for educational purposes or simple toy applications where full 8-bit or wider SECDED is not required.

Choose Open in IDE. RTL Studio loads the packaged workspace for SECDED Nibble Syndrome (toy) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Toy SECDED syndrome calculator for 4-bit nibbles with invalidate and shadow commit support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

The module operates with the following ports:

Port	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`en`	Input	1	Enable signal
`invalidate`	Input	1	Invalidate stored data
`shadow_commit`	Input	1	Commit shadow data to main memory
`data_in`	Input	4	Data input
`shadow_data_in`	Input	4	Shadow data input
`byte_en`	Input	2	Byte enable mask (00=disable, 01=LSB, 10=MSB, 11=all)
`data_out`	Output	4	Decoded data output
`syndrome`	Output	2	Syndrome output (lower 2 bits of 3-bit syndrome)
`valid`	Output	1	Data validity flag
`err`	Output	1	Error detection flag

Architecture

The design uses a 7-bit SECDED codeword stored in an internal register. The codeword format is {P2, P1, D3, P0, D2, D1, D0}.

Parity bits are calculated as follows:

P0 covers D0, D1, and D3.
P1 covers D0, D2, and D3.
P2 covers D1, D2, and D3.

The syndrome is calculated by comparing stored parity bits with recomputed parity bits from the stored data. The err flag is asserted if the syndrome is non-zero and the valid flag is high.

Verification

The testbench verifies basic write, invalidate, shadow commit, byte enable hold, and reset functionality.

### Test Cases

Test Case	Description	Result
TC1	Basic Write and Read	PASS
TC2	Invalidate	PASS
TC3	Shadow Commit	PASS
TC4	Byte Enable Hold	PASS
TC5	Syndrome for Valid Data	PASS
TC6	Reset	PASS

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