RTL Studio Open IDE

Wiki Handshakes Valid / ready

Valid / ready

Transfer on valid && ready; do not drop a beat while stalled.

A beat commits when both valid and ready are 1 in the same cycle. The source must hold payload while valid && !ready.

sequenceDiagram
  participant S as src
  participant D as dst
  S->>D: valid+data
  Note over D: not ready
  S->>D: hold
  D->>S: ready
  Note over S,D: transfer
wire fire = valid && ready;

Wrong vs right

Wrong — change data the cycle after valid rose while ready is still 0.

Right — register the payload with valid, update only on fire or when idle.

See also