Coverage answers “did we hit the interesting cases?” A covergroup samples coverpoints. Some simulators (including browser Verilator flows) need manual bins instead of full IEEE covergroups.
flowchart TB stim[stimulus] --> dut[DUT] dut --> sample[sample bins] sample --> hit[coverage_report]
int hit_full, hit_empty, n;
always @(posedge clk) begin
if (full) hit_full++;
if (empty) hit_empty++;
n++;
end
Or a real covergroup when the engine supports it:
covergroup cg @(posedge clk);
cp_full: coverpoint full { bins b[] = {0, 1}; }
endgroup
Close loops: constrained-random fills holes the directed test missed.
Wrong vs right
Wrong — 100% code coverage and no FIFO-full hit.
Right — name the protocol corners (full, empty, back-to-back) as explicit bins or counters.