Wiki SystemVerilog always_comb and always_ff

always_comb and always_ff

Explicit combo vs flop processes that lint can check.

SV process kinds document intent. Tools can flag a flop written as always_comb and a combo block that infers a latch.

flowchart LR
  ac[always_comb] --> combo[gates]
  af[always_ff] --> flops[FFs]

always_comb y = a ^ b;

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) q <= '0;
  else        q <= d;
end

always @(*) still works; always_comb additionally runs at time 0 and is stricter about sensitivity.

Wrong vs right

Wrong — always @(posedge clk) with a missing reset branch you meant to have, and blocking assigns.

Right — always_ff + NBA + explicit reset/enable.