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Wiki SystemVerilog Associative arrays

Associative arrays

Sparse maps keyed by index type for TB memory models.

An associative array (type a[index_t]) stores only written keys. Good for sparse memories and lookup tables in the testbench.

flowchart LR
  key[addr] --> map["byte mem[int]"]
  map --> val[data]
byte mem[int];          // int key
bit exists;
mem[32'h1000] = 8'h5A;
exists = mem.exists(32'h1000);

Pick the index type on purpose (int, string, bit [31:0]). Iterate with first / next. Dense, addressed RAM in RTL stays a packed unpacked array.

Wrong vs right

Wrong — logic [7:0] ram [bit [31:0]] as synthesizable on-chip SRAM.

Right — associative arrays in the TB; inferred reg [7:0] ram [0:1023] in the DUT.

See also