RTL Studio Open IDE

Wiki SystemVerilog Constrained random

Constrained random

rand fields, randomize(), and constraint blocks for legal stimulus.

Mark fields rand, call randomize(), and constrain the legal space so you do not emit junk protocols.

flowchart LR
  randf[rand_fields] --> rz[randomize]
  cz[constraint] --> rz
  rz --> legal[legal_txn]
class fifo_item;
  rand bit        we;
  rand bit [7:0]  data;
  constraint c_mix { we dist { 1 := 70, 0 := 30 }; }
endclass

fifo_item it = new();
if (!it.randomize()) $fatal("randomize failed");

dist, implications ->, and soft constraints steer coverage. Always check the randomize() return value.

Wrong vs right

Wrong — unconstrained rand bit [31:0] addr on a 256-deep memory (mostly unmapped).

Right — addr inside {[0:255]}; plus a mix dist for reads vs writes.

See also