RTL Studio Open IDE

Wiki SystemVerilog Interfaces and modports

Interfaces and modports

Bundle a bus once; modports name master vs slave directions.

An interface is a named bundle of signals. A modport is a view: which side drives valid, which side drives ready.

flowchart LR
  m[master] --> ifc[axi_if]
  ifc --> s[slave]
interface simple_if (input logic clk);
  logic valid, ready;
  logic [7:0] data;
  modport src (output valid, data, input ready);
  modport dst (input valid, data, output ready);
endinterface

Wrong vs right

Wrong — copy 20 AXI ports through every hierarchy level by hand.

Right — one interface instance, modport at each end, and a clocking/TB view later if you need it.

See also