SystemVerilog string is a dynamic character array for testbench text — not a synthesizable wire. $sformatf builds a formatted string without printing it.
flowchart LR vals[values] --> fmt["$sformatf"] fmt --> s[string] s --> log["$display / uvm_info"]
string msg;
msg = $sformatf("cycle %0d data=%02h", cyc, data);
$display("%s", msg);
Prefer %0d / %0h so widths do not pad blindly. Keep DUT ports as logic buses; format only in the TB or UVM report macros.
Wrong vs right
Wrong — declare a DUT output as string.
Right — log with $sformatf in the testbench; drive bits on the interface.