Wiki SystemVerilog typedef, enum, and struct

typedef, enum, and struct

Named types for FSM states and packed protocol fields.

Name the bits. enum beats magic state numbers; packed struct beats a pile of slices.

flowchart LR
  enum[state_enum] --> fsm[FSM]
  struct[packed_struct] --> pkt[packet]

typedef enum logic [1:0] { ST_IDLE, ST_RUN, ST_DONE } state_t;

typedef struct packed {
  logic       we;
  logic [3:0] addr;
  logic [7:0] data;
} cmd_t;

Wrong vs right

Wrong — logic [1:0] state with comments that drift.

Right — state_t state_q plus unique case (state_q).

Wrong vs right

See also