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Wiki SystemVerilog Packed vs unpacked

Packed vs unpacked

How array layout changes slicing, width, and RAM inference.

Packed arrays are a single vector (bit-select, concat, math). Unpacked arrays are a collection of elements (memories, queues of words).

flowchart TB
  packed["logic [3:0][7:0] p"] --> bits[bit_select]
  unpacked["logic [7:0] u [0:3]"] --> words[word_select]
logic [3:0][7:0] packed_bytes;   // 32-bit vector
logic [7:0]      mem [0:15];     // 16 words of 8

mem[i] is a word. packed_bytes[i] is a byte slice of one vector. Mixing them in a port is a common type error.

Wrong vs right

Wrong — treat an unpacked RAM as a concat-able bus.

Right — packed for datapath fields; unpacked for memory arrays (mem[addr]).

See also