Arbiters
Fixed-Priority Arbiter with Grant Mask
A 4-input fixed-priority arbiter with a grant mask to disable specific requests dynamically.
About this block
Simulate it in the Verilog IDE
Fixed-Priority Arbiter with Grant Mask is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a 4-input fixed-priority arbiter with a dynamic grant mask.
It selects the highest-priority active request that is not masked.
Priority order is strictly req[3] > req[2] > req[1] > req[0].
- Choose Open in IDE. RTL Studio loads the packaged workspace for Fixed-Priority Arbiter with Grant Mask.
- Read the Verilog module in the editor. The catalog line for this block: A 4-input fixed-priority arbiter with a grant mask to disable specific requests dynamically.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Interface
The module uses the following ports:
| Port | Direction | Width | Description |
|---|---|---|---|
req | Input | 4 | Request signals from four masters. 1 = active request. |
mask | Input | 4 | Mask signals. 0 disables the corresponding request (ignores it). 1 enables it. |
grant | Output | 4 | Grant signal. One-hot encoding of the winning request. |
Architecture
The design uses a simple combinational priority encoder structure. It checks requests from highest priority (bit 3) to lowest (bit 0). Each request is logically ANDed with its corresponding mask bit. The first unmasked active request receives the grant. All other grant bits remain zero.
Verification
The testbench covers eight specific scenarios to ensure correctness. All tests passed successfully during simulation.
| Test Case | Description | Expected Grant | Result |
|---|---|---|---|
| TC1 | No requests active | 0000 | PASS |
| TC2 | Single request req[0] | 0001 | PASS |
| TC3 | All requests active | 1000 | PASS |
| TC4 | Mask req[3], req[2] active | 0100 | PASS |
| TC5 | Mask req[3:1], req[0] active | 0001 | PASS |
| TC6 | All requests masked | 0000 | PASS |
| TC7 | Mask req[1], req[3] and req[0] active | 1000 | PASS |
| TC8 | Mask req[3] and req[1], req[0] active | 0001 | PASS |
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