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Weighted Round-Robin Arbiter 4 — L2 Upgrade

4-input Weighted Round-Robin Arbiter with masking and Park-on-Grant strategy.

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Weighted Round-Robin Arbiter 4 — L2 Upgrade is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4-input Park-on-Grant Round-Robin Arbiter with individual request masking.

Important Note on "Weighted": Despite the title, this specific implementation performs a linear search based on the Park-on-Grant state. It does not implement variable weights (1, 2, 3, 4). It selects the first eligible request in the circular window starting from the last granted ID. For true weighted arbitration, the search logic would need modification.

### Key Characteristics

  • Inputs: 4 Request lines (req[3:0])
  • Masking: Individual enable/disable per request line (mask[3:0])
  • Strategy: Park-on-Grant (Search starts at last granted ID)
  • Logic Type: Combinational search logic with registered outputs
  • Output: One-hot grant signal (grant[3:0]) and validity flag (valid)
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Weighted Round-Robin Arbiter 4 — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 4-input Weighted Round-Robin Arbiter with masking and Park-on-Grant strategy.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 4-Input Arbitration: Handles up to 4 concurrent requesters.
  • Masking Support: Allows specific requesters to be disabled dynamically via the mask input.
  • Park-on-Grant Behavior: Prevents starvation of persistent requesters by keeping the search window anchored to the last granted ID.
  • Combinational Decision: The grant decision is made in combinational logic, ensuring minimal latency, while outputs are registered for stability.
  • Idle Handling: If no requests are eligible, valid is deasserted, and the state remains unchanged.

Ports

PortDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
reqInput[3:0]Request signals (1=active)
maskInput[3:0]Mask signals (0=disabled, 1=enabled)
grantOutput[3:0]Grant signals (one-hot, 1=granted)
validOutput1Valid signal (high when grant is asserted)

Integration

  1. Instantiation: Include rtl/weighted_rr_mask_park_4.v in your project.
  2. Clocking: Ensure clk is stable. rst_n should be asserted low during initialization.
  3. Simulation:

- Standard Verilog Simulator: Compile rtl/weighted_rr_mask_park_4.v and tb/tb_weighted_rr_mask_park_4.v. - Waveform Inspection: Use your simulator's waveform viewer (e.g., VCD, FSDB, WLF) to inspect signals. - Verification: Run the testbench to verify functionality against expected pass conditions.

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