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Lock-Free N-Input Arbiter with Backpressure

A lock-free arbiter that grants access to the lowest-priority active request and holds the grant until acknowledgment, supporting backpressure.

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About this block

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Mediumsystemverilogsimsyn

Lock-Free N-Input Arbiter with Backpressure is a SystemVerilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a lock-free N-input arbiter with backpressure support. It uses a simple two-state finite state machine to manage grant cycles. The arbiter prioritizes the lowest-indexed request when multiple inputs are active. It holds the grant signal until the corresponding channel acknowledges receipt. The busy output indicates when the arbiter is waiting for an acknowledgment.

This lock-free arbiter provides a robust solution for managing multiple input requests. It guarantees fair priority based on bit index and supports backpressure. The design is simple, efficient, and fully verified.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Lock-Free N-Input Arbiter with Backpressure.
  2. Read the SystemVerilog module in the editor. The catalog line for this block: A lock-free arbiter that grants access to the lowest-priority active request and holds the grant until acknowledgment, supporting backpressure.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Lock-free operation: Ensures no deadlock conditions by using a simple state machine.
  • Backpressure support: Holds the grant signal until an acknowledgment is received from the specific channel.
  • Priority encoding: Favors the lowest bit index (bit 0 has highest priority).
  • Synchronous design: Uses a single clock domain and synchronous reset.
  • Verified: Verified with Verilator simulation.

Architecture

The design consists of a combinational priority encoder and a sequential state machine.

  1. Priority Encoder: In the IDLE state, if any request is active, the lowest-indexed bit is selected using the expression req & (~req + 1).
  2. State Machine: Transitions between IDLE and WAIT_ACK states.

- IDLE: Checks for active requests. If present, calculates the grant mask and transitions to WAIT_ACK. - WAIT_ACK: Waits for the specific channel to acknowledge. If the acknowledgment matches the current grant, it returns to IDLE. Otherwise, it holds the grant and remains in WAIT_ACK.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
reqInput4Request inputs from 4 channels
grantOutput4Grant outputs to 4 channels
ackInput4Acknowledge inputs from 4 channels
busyOutput1High when waiting for acknowledgment

Verification

The testbench covers four key scenarios to ensure correctness:

  1. Single Request: Verifies proper grant/ack behavior for a single active request.
  2. Priority Selection: Verifies that the lowest bit index is selected when multiple requests are active.
  3. Backpressure: Verifies that the grant is held if no acknowledgment is received.
  4. Rapid Succession: Verifies handling of rapid request/grant cycles.

### Running Simulation

To verify the design, use Verilator:

Expected Output: The simulation log should end with:

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