Arbiters
4-Channel Oldest-First (FIFO) Arbiter — L2 Upgrade
4-Channel Oldest-First (FIFO) Arbiter with almost-full flag and flush support.
About this block
Simulate it in the Verilog IDE
4-Channel Oldest-First (FIFO) Arbiter — L2 Upgrade is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements a 4-channel oldest-first arbiter with an "almost-full" flag and flush support.
It prioritizes the lowest index among valid requests to ensure FIFO-like ordering.
The grant signal is registered and cleared when backpressure is applied.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Channel Oldest-First (FIFO) Arbiter — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: 4-Channel Oldest-First (FIFO) Arbiter with almost-full flag and flush support.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Interface
| Signal | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low asynchronous reset |
| valid | Input | 4 | Valid request signals per channel |
| ready | Input | 4 | Ready acknowledgment signals per channel |
| grant | Output | 4 | Granted channel signal (one-hot) |
| almost_full | Output | 1 | Asserted when >= 3 channels are valid |
| flush_ack | Output | 1 | Flush acknowledgment status (currently 0) |
Architecture
The arbiter uses combinational logic to determine the oldest request based on channel index (0 is highest priority). The grant register updates only when backpressure is not applied (i.e., at least one channel is ready). If all channels are busy (backpressure), the grant is cleared.
The almost-full logic checks all combinations of three valid channels. If any combination of three or more channels is valid, the flag asserts.
Verification
The testbench verifies reset state, single request, oldest-first priority, almost-full flags, and backpressure handling. All seven test cases passed successfully in the simulation log. The simulation was run using Icarus Verilog with VCD dump for waveform analysis.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset state check | PASS |
| TC2 | Single request (Channel 0) | PASS |
| TC3 | Multiple requests (Oldest-First) | PASS |
| TC4 | Almost-full check (3 channels) | PASS |
| TC5 | Almost-full check (2 channels) | PASS |
| TC6 | Backpressure handling | PASS |
| TC7 | Flush-ack zero check | PASS |
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