Arbiters

Sticky RR Hold Arbiter 4

A 4-channel sticky round-robin arbiter that holds the grant until acknowledgment, then advances the pointer.

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About this block

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Sticky RR Hold Arbiter 4 is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a sticky round-robin arbiter for four request lines. It ensures fair access by rotating the grant priority, but uniquely holds the grant signal active until the corresponding master asserts an acknowledge (ack) signal. This prevents grant loss during slow acknowledgment cycles or when masters require multiple cycles to process data.

### Key Characteristics

Sticky Grant: The grant remains asserted until ack is received.
Round-Robin Rotation: After acknowledgment, the pointer advances to the next requesting master.
Fairness: Prevents starvation by ensuring all masters get a turn.
Synthesizable: Standard ASIC/FPGA compatible Verilog.

Choose Open in IDE. RTL Studio loads the packaged workspace for Sticky RR Hold Arbiter 4.
Read the Verilog module in the editor. The catalog line for this block: A 4-channel sticky round-robin arbiter that holds the grant until acknowledgment, then advances the pointer.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports four independent request inputs (req[3:0]).
Provides a single-hot grant output (grant[3:0]).
Hold Mechanism: Grant is not de-asserted until the specific ack bit is high.
Pointer Advancement: The internal pointer only rotates after a successful handshake (req + ack).
Reset Behavior: Clears all state and grants to default position on active-low reset.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	System clock
`rst_n`	Input	1	Active-low asynchronous reset
`req`	Input	4	Request signals from masters (active high)
`ack`	Input	4	Acknowledge signals from masters (active high)
`grant`	Output	4	Granted request signals (single-hot, active high)

Architecture

The design uses a 2-bit pointer (ptr) to track the current arbitration priority position.

Combinational Logic: Determines the next grant based on current requests, the current pointer, and the hold status.
State Machine:

- If no grant is active, it grants the master at ptr. - If a grant is active, it holds it until ack[ptr] is asserted. - Upon ack, the pointer rotates to find the next active request.

Sequential Logic: Registers update on the positive edge of clk or upon reset.

### High-Level Flow

Verification

The testbench (tb_sticky_round_robin_hold_4.v) verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset Behavior	Grant and Pointer clear to 0
TC2	Single Request	Correct grant to requesting master
TC3	Hold Grant	Grant stays active during ack cycle
TC4	Advance	Pointer advances after ack
TC5	Priority	Current pointer has priority over others
TC6	Rotation	Next request granted after ack
TC7	Wrap-Around	Pointer wraps from 3 to 0 correctly

All test cases pass successfully. Run the simulation to view waveforms and log output.

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