Arbiters

2-Request Static Priority Grant

A combinational static priority arbiter for two request lines where req0 has higher priority than req1.

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2-Request Static Priority Grant is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a static priority arbiter for two request lines. It is a simple, low-latency combinational logic module suitable for systems requiring deterministic arbitration between two masters.

This IP provides a simple, low-latency static priority arbiter.

Priority: Request 0 (req0) holds the highest priority.
Behavior: If both requests are active, req0 wins the grant.
Output: The valid output indicates if any request is asserted.
Logic: Pure combinational logic with no clock dependency.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Request Static Priority Grant.
Read the Verilog module in the editor. The catalog line for this block: A combinational static priority arbiter for two request lines where req0 has higher priority than req1.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

Signal	Direction	Width	Description
`req0`	Input	1	Request 0 (Highest Priority)
`req1`	Input	1	Request 1 (Lowest Priority)
`grant`	Output	2	Grant vector `[1:0]`. `2'b01` for req0, `2'b10` for req1, `2'b00` for idle.
`valid`	Output	1	Valid indicator (1 if any request is active)

Architecture

The design uses combinational logic to resolve priority. The logic is defined as follows:

grant[0] = req0 (req0 always wins if active)
grant[1] = req1 & ~req0 (req1 wins only if req0 is inactive)
valid = req0 | req1 (Active if either request is high)

Verification

The testbench (tb/tb_static_grant_2.v) covers all four input combinations.

Test Case	req0	req1	Expected Grant	Expected Valid	Result
TC1 Idle	0	0	2'b00	0	PASS
TC2 req0	1	0	2'b01	1	PASS
TC3 req1	0	1	2'b10	1	PASS
TC4 Both	1	1	2'b01	1	PASS

### Running Simulation

Run the simulation.
Check the Log panel for the following output:
Use the RtlStudio Waveform tab with sim/dump.vcd to inspect signals.

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