RTL Studio Open IDE

Arbiters

2-Request Lock-Until-Idle Arbiter

A synchronous arbiter that locks the grant to the winning request until that request deasserts, with a fixed tie-break preference for request 0.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

2-Request Lock-Until-Idle Arbiter is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A synchronous, lock-until-idle arbitration IP for two request lines. This module ensures exclusive access to a shared resource by holding the grant signal until the winning request deasserts.

This arbiter provides simple, deterministic locking for two requests. It is suitable for low-latency shared resource access where fairness is not required, but exclusive access is critical. The tie-break preference is fixed to req[0].

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Request Lock-Until-Idle Arbiter.
  2. Read the Verilog module in the editor. The catalog line for this block: A synchronous arbiter that locks the grant to the winning request until that request deasserts, with a fixed tie-break preference for request 0.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Lock-Until-Idle: The grant remains asserted until the winning request deasserts.
  • Two Inputs: Supports two independent request lines (req[0], req[1]).
  • Tie-Breaking: If both requests are active simultaneously, req[0] takes priority.
  • Synchronous Operation: Operates on the positive edge of clk with asynchronous active-low reset.
  • Valid Indicator: Outputs a valid signal when any request is active.

Ports

PortDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
reqInput2Request vector [1:0]
grantOutput2Grant vector [1:0]
validOutput1Valid indicator (high if any request is active)

Verification

The provided testbench (tb_lock_until_idle_2.v) covers ten specific scenarios to verify functionality:

  1. Idle Check: Verifies valid is low when no requests are active.
  2. Single Request Grants: Validates grants for req[0] and req[1] individually.
  3. Lock Hold: Confirms the lock is held while the request remains active.
  4. Release: Verifies the lock is released when the request deasserts.
  5. Tie-Breaking: Tests simultaneous requests to ensure req[0] wins.
  6. Stability: Ensures correct behavior when one request drops while the other is locked.

### Running Simulation

To run the simulation, ensure you have Icarus Verilog installed (or adjust for your simulator):

Expected Output:

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