Arbiters

Token-Ring Arbiter 4

A 4-input token-ring arbiter that rotates a one-hot grant token to the next active requester, ensuring fair access.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Token-Ring Arbiter 4 is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 4-input Token-Ring Arbiter in Verilog.

It provides fair, round-robin access to a shared resource among four requesters using a rotating one-hot token mechanism.

The design ensures deterministic, starvation-free arbitration and is fully verified and synthesis-ready.

Choose Open in IDE. RTL Studio loads the packaged workspace for Token-Ring Arbiter 4.
Read the Verilog module in the editor. The catalog line for this block: A 4-input token-ring arbiter that rotates a one-hot grant token to the next active requester, ensuring fair access.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Fair Arbitration: Round-robin access ensures equitable distribution of resource access.
Low Latency: Combinational grant logic provides immediate response to active requests.
Synthesis Ready: Verified for standard CMOS processes.
Comprehensive Verification: 7 test cases covering reset, single/multi-request, and rotation scenarios.
Deterministic: No priority encoding; strictly follows token rotation.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
req	Input	4	Request signals [3:0]
grant	Output	4	Grant signals [3:0]

Architecture

The design consists of a sequential token register and combinational logic for next-token calculation and grant generation.

Token Register: Updates on the positive edge of clk. Initialized to 4'b0001 (position 0) on reset.
Next Token Logic: Prioritizes requests from req[0] to req[3]. If no requests are active, the token rotates to the next position.
Grant Logic: Bitwise AND of the current token register and the request vector.

Verification

The testbench validates the following scenarios using Icarus Verilog:

Test Case	Description	Result
TC1	Reset state check	PASS
TC2	Single request at req[0]	PASS
TC3	Rotate to req[1]	PASS
TC4	Req at rotated token	PASS
TC5	Multiple requests	PASS
TC6	No requests rotation	PASS
TC7	Token at position 3	PASS

All test cases passed successfully. A VCD waveform is generated for inspection.

Integration

To integrate this IP into your design:

Include rtl/token_ring_arbiter_4.v in your project.
Instantiate the module:
Connect your request and grant signals to the arbiter ports.

Limitations

Single Clock Domain: This IP assumes a single clock domain. For cross-clock domain applications, additional synchronization logic is required.
Priority: If multiple requests are active, the arbiter prioritizes lower-indexed requests (req[0] > req[1] > req[2] > req[3]) only if the token is not currently aligned with a higher-indexed active request. However, the token rotation ensures long-term fairness.

More in Arbiters

All Arbiters blocks