Arbiters

4-Request Masked Priority Grant

A 4-bit priority grant module that selects the lowest-index active request after applying a mask.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

4-Request Masked Priority Grant is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 4-bit masked priority grant module.

It selects the lowest-index active request among unmasked inputs using combinational logic for immediate response.

The design is fully verified and ready for integration into arbitration systems requiring selective request handling.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Request Masked Priority Grant.
Read the Verilog module in the editor. The catalog line for this block: A 4-bit priority grant module that selects the lowest-index active request after applying a mask.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

The module provides the following ports:

Port	Direction	Width	Description
req	Input	[3:0]	Request signals
mask	Input	[3:0]	Mask control signals (1=Masked, 0=Active)
grant	Output	[3:0]	Granted request signal (one-hot)
valid	Output	1	Valid output flag (1 if any unmasked request is active)

Architecture

The design consists of two main stages:

Masking: The request vector is masked using bitwise NOT and AND operations. A mask bit of 1 disables the corresponding request.
Priority Encoding: A fixed-priority encoder selects the lowest index from the masked requests. Priority is defined as bit 0 > bit 1 > bit 2 > bit 3.

Verification

The testbench verifies eight specific scenarios covering edge cases and masking logic. All tests passed successfully in simulation.

Test Case	Description	Result
TC1	No requests active	PASS
TC2	Single request bit 0	PASS
TC3	Multiple requests, no mask	PASS
TC4	Mask out bit 0	PASS
TC5	Mask out bits 0 and 1	PASS
TC6	Mask all requests	PASS
TC7	Mask higher priority request	PASS
TC8	Only highest request active	PASS

More in Arbiters

All Arbiters blocks