Arbiters

Matrix Arbiter 4-Port

4-port Least-Recently-Granted matrix arbiter with round-robin fairness.

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Matrix Arbiter 4-Port is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A 4-port Least-Recently-Granted (LRG) matrix arbiter implemented in Verilog. This IP provides fair round-robin style arbitration for four request lines, ensuring that no single requester is starved during contention.

This IP provides a robust and fair arbitration solution for 4-port systems.

It is suitable for bus interfaces and resource sharing applications where deterministic fairness is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for Matrix Arbiter 4-Port.
Read the Verilog module in the editor. The catalog line for this block: 4-port Least-Recently-Granted matrix arbiter with round-robin fairness.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-Port Support: Handles up to 4 concurrent requestors.
LRG Policy: Implements Least-Recently-Granted arbitration to ensure fairness.
Deterministic: Combinational decision logic with registered output ensures predictable behavior.
Verified: Comprehensive testbench coverage included.

Interface

Signal	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`req`	Input	4	Request inputs `[3:0]`
`grant`	Output	4	Grant outputs `[3:0]`

Architecture

The arbiter uses a preference matrix logic to determine the next grant. When a requestor is granted, its preference is rotated to the least preferred position. This mechanism guarantees fairness across all four ports.

Verification

The testbench validates reset behavior, single requests, and contention scenarios.

Test Case	Description	Result
TC1	Reset Test	PASS
TC2	Single Request	PASS
TC3	Contention Priority	PASS
TC4	LRG Update Sequence	PASS
TC5	Fairness Check	PASS

Simulation is performed using Icarus Verilog. VCD dump files are generated for waveform analysis.

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