Arbiters

Weighted Priority Arbiter (4 req) — L2 Upgrade

Weighted Priority Arbiter with Mask, Park, and Hold Lock for 4 requests.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Weighted Priority Arbiter (4 req) — L2 Upgrade is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a flexible 4-way weighted priority arbiter with dynamic masking, park mode, and hold lock capabilities.

It is implemented in Verilog and targets L2 complexity.

The design ensures deterministic arbitration based on a strict priority hierarchy: Hold Lock > Park Mode > Weighted Priority.

Dynamic Masking: Specific requests can be disabled via the mask input. Note: mask[i]=1 enables request i, mask[i]=0 disables it.
Weighted Priority: When multiple requests are active, priority is determined by the weight input. Higher weight wins. If weights are equal, the higher ID wins.
Park Mode: Forces the grant to a specific ID (park_id) when park_en is asserted, provided the parked ID is requesting.
Hold Lock: Preserves the current grant during high-priority events or when hold_lock is asserted.

Choose Open in IDE. RTL Studio loads the packaged workspace for Weighted Priority Arbiter (4 req) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Weighted Priority Arbiter with Mask, Park, and Hold Lock for 4 requests.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
req	Input	[3:0]	Request signals
mask	Input	[3:0]	Mask to disable requests (1=enabled, 0=disabled)
weight	Input	[3:0]	Weight for priority resolution (higher value = higher priority)
park_en	Input	1	Enable park mode
park_id	Input	[1:0]	Park target ID (0-3)
hold_lock	Input	1	Hold current grant
gnt	Output	[3:0]	Grant signal (one-hot)
busy	Output	1	Busy indicator (1 if any request is pending/granted)

Verification

The testbench covers basic requests, masking, weight priority, park mode, hold lock, and reset. All test cases passed successfully.

Test Case	Description	Result
TC1	Basic Single Request	PASS
TC2	Masking	PASS
TC3	Weight Priority	PASS
TC4	Park Mode	PASS
TC5	Hold Lock	PASS
TC6	Complex Weight/Mask	PASS
TC7	Reset Behavior	PASS

To run the simulation:

Ensure Icarus Verilog is installed.
Run make sim in the project root.
Check the log for INFO: PASS.

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