Arbiters

4-Channel Round-Robin Arbiter with Priority Rotation

A 4-channel round-robin arbiter with priority rotation to ensure fair access to shared resources.

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4-Channel Round-Robin Arbiter with Priority Rotation is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 4-channel round-robin arbiter with priority rotation. It ensures fair access to a shared resource among four requesters by rotating the priority pointer to the next channel after each grant is issued. This mechanism prevents starvation and maintains equitable service distribution.

This IP provides a robust, synthesizable round-robin arbitration solution suitable for bus masters or peripheral controllers. It features four independent request lines, combinational logic for immediate grant determination, and sequential logic for priority pointer rotation. The design includes synchronous reset capability and is verified via a comprehensive testbench.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Channel Round-Robin Arbiter with Priority Rotation.
Read the Verilog module in the editor. The catalog line for this block: A 4-channel round-robin arbiter with priority rotation to ensure fair access to shared resources.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-Channel Support: Handles four independent request lines.
Fair Arbitration: Implements round-robin priority rotation to prevent starvation.
Low Latency: Uses combinational logic for immediate grant determination.
Synchronous Control: Includes a synchronous reset to initialize the priority pointer.
Valid Signal: Provides a valid output to indicate when a grant is asserted.

Interface

The module interface is defined as follows:

Signal	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low reset
`req`	input	4	Request signals [3:0]
`grant`	output	4	Grant signals [3:0]
`valid`	output	1	Valid output

Architecture

The arbiter uses a priority pointer to track the next starting channel. The combinational logic checks requests starting from the priority pointer in a circular manner, selecting the first active request found. The sequential logic updates the pointer to the next channel after a grant is issued.

Verification

The testbench verifies single requests, priority rotation, no-request behavior, and reset behavior. All test cases passed successfully in simulation.

Test Case	Description	Result
TC1	Single Request	PASS
TC2	Priority Rotation	PASS
TC3	No Requests	PASS
TC4	Reset Behavior	PASS

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