Arbiters

4-Input Sliding Window Arbiter — L2 Upgrade

A 4-input sliding window arbiter with weighted priority, masking, parking, and hold capabilities for fair resource allocation.

Open in IDE Category

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

4-Input Sliding Window Arbiter — L2 Upgrade is a Verilog reference block in the Arbiters catalog. Round-robin, fixed-priority, and grant-based resource arbiters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4-input sliding window arbiter with weighted priority, masking, parking, and hold capabilities.

It rotates a priority window to ensure fair access among requestors.

High-priority requests are served based on the current window position.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Input Sliding Window Arbiter — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 4-input sliding window arbiter with weighted priority, masking, parking, and hold capabilities for fair resource allocation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports 4 concurrent request inputs.
Implements sliding window algorithm for round-robin fairness.
Configurable weight via window rotation.
Bitwise masking for request filtering.
Park mode for deterministic idle behavior.
Hold mode for state preservation.
Synchronous reset with active-low polarity.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low synchronous reset
req	Input	[3:0]	Request signals from 4 masters
mask	Input	[3:0]	Mask bits to disable specific requests
park	Input	[3:0]	Park bits to force grant on idle
hold	Input	1	Hold signal to freeze grant
gnt	Output	[3:0]	Grant signals to 4 masters
valid	Output	1	Valid flag indicating active grant

Architecture

The arbiter uses a sliding window to determine priority. Window bit 1 indicates high priority for the corresponding request. Window bit 0 indicates low priority for the corresponding request. On each clock cycle, the window rotates left if a grant was previously issued. Requests are evaluated against the current window position. Masked requests are ignored during evaluation. Parked requests are granted if no other requests are active. Hold mode prevents window rotation and grant updates.

Integration

To integrate this IP into your design:

Include sliding_window_arbiter_4_weight_mask.v in your project.
Instantiate the module with your clock, reset, and request signals.
Configure mask, park, and hold signals as needed for your application.
Connect the gnt and valid outputs to your downstream logic.

Verification

The testbench verifies basic functionality, masking, parking, hold, and reset. All test cases passed successfully in simulation. Simulation was performed using Icarus Verilog. VCD dump is available for waveform analysis.

Test Case	Description	Result
TC1	Basic single request	PASS
TC2	Masking functionality	PASS
TC3	Park mode	PASS
TC4	Hold mode	PASS
TC5	Weighted priority sliding	PASS
TC6	Reset behavior	PASS

More in Arbiters

All Arbiters blocks