LFSR, PRBS & CRC

Additive Lagged Fibonacci 16

A 16-bit Additive Lagged Fibonacci pseudo-random number generator with taps j=3 and k=5.

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About this block

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Additive Lagged Fibonacci 16 is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 16-bit Additive Lagged Fibonacci Pseudo-Random Number Generator (PRNG). The generator uses taps $j=3$ and $k=5$ to produce pseudo-random sequences. The output is calculated as:

$$ x[n] = (x[n-3] + x[n-5]) \mod 2^{16} $$

This design is lightweight, suitable for embedded systems, and provides reproducible sequences via seed loading.

Choose Open in IDE. RTL Studio loads the packaged workspace for Additive Lagged Fibonacci 16.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit Additive Lagged Fibonacci pseudo-random number generator with taps j=3 and k=5.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Parallel Data Path: Full 16-bit precision for state and output.
Synchronous Reset: Resets all internal state registers to zero.
Seed Loading: Allows initialization with a specific 16-bit seed for reproducibility.
Simple Logic: Uses basic combinatorial addition and shift register logic.
Low Resource Utilization: Minimal LUT/FF usage, ideal for resource-constrained FPGAs.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`seed_in`	Input	16	Seed value for initialization
`seed_load`	Input	1	Active-high signal to load seed into state
`rand_out`	Output	16	Current pseudo-random output value

Architecture

The module maintains a 5-stage shift register for state storage. Each stage holds a 16-bit value representing previous outputs. The next state is computed by adding the values from taps 3 and 5 (indices 2 and 4 in 0-based indexing).

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset Check	Output is 0 after reset
TC2	Seed Load Check	Output matches seed
TC3	PRNG Variation Check	Output changes from seed
TC4	Non-Zero Output Check	Output is not all zeros

### Running Simulation

Compile the RTL and testbench.
Run the simulation.
Check the Log panel for:

- INFO: TC1 Reset check PASS - INFO: TC2 Seed load check PASS - INFO: TC3 PRNG variation PASS - INFO: TC4 PRNG dynamic output PASS - INFO: PASS

Inspect waveforms using sim/dump.vcd in your waveform viewer (e.g., RtlStudio Waveform tab).

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