LFSR, PRBS & CRC

PRBS-32 Sequence Checker with Error Counter

A SystemVerilog module that checks incoming data against a PRBS32 sequence generated by an LFSR. It counts bit errors and asserts a persistent error flag.

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About this block

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Mediumsystemverilogsimsyn

PRBS-32 Sequence Checker with Error Counter is a SystemVerilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP implements a PRBS-32 sequence checker with an error counter. It validates incoming data against a generated PRBS32 sequence. The module counts bit errors and asserts a persistent error flag.

The design uses a Linear Feedback Shift Register (LFSR) to generate the expected PRBS32 sequence. It compares the input data stream with the LFSR output on every valid cycle. A registered mismatch signal drives both the error flag and the error counter. The error counter supports asynchronous reset via a clear signal.

This IP provides a robust solution for PRBS32 integrity checking. It is suitable for high-speed serial link validation and loopback testing. The design is simple, synchronous, and fully verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for PRBS-32 Sequence Checker with Error Counter.
Read the SystemVerilog module in the editor. The catalog line for this block: A SystemVerilog module that checks incoming data against a PRBS32 sequence generated by an LFSR. It counts bit errors and asserts a persistent error flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Implements PRBS32 polynomial: x^32 + x^7 + x^3 + x^2 + 1.
Taps are located at bits 31, 7, 3, and 2 of the LFSR state.
Supports 32-bit parallel data input with valid strobe.
Provides a persistent error flag for immediate fault detection.
Includes a 16-bit error counter with clear capability.
Fully synchronous design with active-low reset.
Verified with seven test cases covering reset, correct data, and error injection.

Ports

Port Name	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Active-low reset signal
data_in	input	32	Input data bus
data_valid	input	1	Data valid strobe
error_flag	output	1	Persistent error flag
error_count	output	16	Error count register
error_count_clear	input	1	Error counter clear signal

Architecture

The following diagram illustrates the internal data flow.

Verification

The testbench verifies the module against seven specific scenarios. Test Case 1 confirms that error_count and error_flag are zero after reset. Test Case 2 verifies that a correct PRBS32 stream produces zero errors. Test Case 3 checks that a single-bit error asserts the error flag and increments the counter. Test Case 4 validates the detection of a burst error consisting of three consecutive mismatches. Test Case 5 ensures the error counter correctly increments to ten after ten errors. Test Case 6 confirms that the error_count_clear signal resets the counter to zero. Test Case 7 verifies correct counting of intermittent errors in a continuous stream. All seven test cases passed successfully in the simulation log.

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