LFSR, PRBS & CRC

Xorshift32 PRNG — L2 Upgrade

32-bit Xorshift pseudo-random number generator with reference-based stall and lock detection.

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Xorshift32 PRNG — L2 Upgrade is a Verilog reference block in the LFSR, PRBS & CRC catalog. LFSR, PRBS, CRC, and pseudo-random sequence generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The xorshift32_prng_lock_detect module implements a 32-bit Xorshift Pseudo-Random Number Generator (PRNG). It is designed for verification environments requiring reproducible random sequences, state monitoring, and robustness against infinite loops.

### Key Features

Algorithm: Standard Xorshift32 (shifts: 13, 17, 5).
Configurable Seeding: Initialize the generator state with a 32-bit seed via the start signal.
Stall Control: Halt state progression when the current state matches a user-defined reference value (ref_val), enabled by compare_en.
Lock Detection: Monitor for repetitive states (where prev_out == current_state) and assert lock_detected if a lock condition persists.
Deterministic: Fully synchronous design with an asynchronous active-low reset (rst_n).
Status Signals: valid indicates when output data is ready; lock_detected indicates a potential infinite loop.

This IP implements a 32-bit Xorshift Pseudo-Random Number Generator (PRNG) with advanced features for verification and debugging. Key capabilities include configurable seeding, reference-value-based stall control, and automatic lock detection to identify repetitive state loops. The design is fully synchronous with an asynchronous reset, ensuring deterministic behavior suitable for rigorous system verification.

Choose Open in IDE. RTL Studio loads the packaged workspace for Xorshift32 PRNG — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 32-bit Xorshift pseudo-random number generator with reference-based stall and lock detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`start`	Input	1	Assert to initialize generator with `seed_in`
`seed_in`	Input	32	Initial seed value for the state register
`compare_en`	Input	1	Enable reference value comparison for stalling
`ref_val`	Input	32	Reference value to trigger stall when matched
`out`	Output	32	Generated pseudo-random value
`valid`	Output	1	High when `out` contains valid data
`lock_detected`	Output	1	High when a repetitive state loop is detected

Architecture

The design consists of two main parts:

Combinational Logic: Implements the Xorshift32 state update function and comparison logic.
Sequential Logic: Manages the state register, running status, and stall/lock flags.

### State Machine

Idle: Waiting for start signal.
Running: On start, the state is initialized to seed_in. Subsequent cycles update the state using Xorshift32 logic.
Stall: If compare_en is high and state == ref_val, the generator stalls, holding the current output.
Lock Detection: If the current state equals the previous output (prev_out), a lock condition is flagged.

Verification

The provided testbench validates the following scenarios:

Test Case	Description	Expected Result
TC1	Basic Seed and Run	`valid` asserted, output is non-zero and changes each cycle.
TC2	Lock Detection / Stall	Generator stalls when `state == ref_val`; `lock_detected` asserts if loop persists.
TC3	Reset Functionality	On `rst_n` low, `valid` and `lock_detected` deassert; state resets.
TC4	Seed Diversity	Different `seed_in` values produce different output sequences.

### Simulation Log Example

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